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Silicon Labs /EFR32BG21B020F768IM32 /HFXO0_S /CFG

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Interpret as CFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (XTAL)MODE 0 (ENXIDCBIASANA)ENXIDCBIASANA 0 (DISABLE)SQBUFSCHTRGANA

MODE=XTAL, SQBUFSCHTRGANA=DISABLE

Description

No Description

Fields

MODE

Crystal Oscillator Mode

0 (XTAL): crystal oscillator

1 (EXTCLK): external sinusoidal clock can be supplied on XI pin.
ENXIDCBIASANA

Enable XI Internal DC Bias
SQBUFSCHTRGANA

Squaring Buffer Schmitt Trigger

0 (DISABLE): undefined

1 (ENABLE): undefined

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data